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1 ds05-11315-1e fujitsu semiconductor data sheet memory cmos 4 m 4 bits fast page mode dynamic ram MB8116400B-50/-60 cmos 4,194,304 4 bits fast page mode dynamic ram n description the fujitsu mb8116400b is a fully decoded cmos dynamic ram (dram) that contains 16,777,216 memory cells accessible in 4-bit increments. the mb8116400b features a ?ast page mode of operation whereby high- speed random access of up to 1,024-bits of data within the same row can be selected. the mb8116400b dram is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory applications where very low power dissipation and high bandwidth are basic requirements of the design. since the standby current of the mb8116400b is very small, the device can be used as a non-volatile memory in equipment that uses batteries for primary and/or auxiliary power. the mb8116400b is fabricated using silicon gate cmos and fujitsus advanced four-layer polysilicon and two- layer aluminum process. this process, coupled with advanced stacked capacitor memory cells, reduces the possibility of soft errors and extends the time interval between memory refreshes. clock timing requirements for the mb8116400b are not critical and all inputs are ttl compatible. n product line & features parameter MB8116400B-50 mb8116400b-60 ras access time 50 ns max. 60 ns max. random cycle time 90 ns min. 110 ns min. address access time 25 ns max. 30 ns max. cas access time 15 ns max. 15 ns max. fast page mode cycle time 35 ns min. 40 ns min. low power dissipation operating current 495 mw max. 412.5 mw max. standby current 11 mw max. (ttl level)/5.5 mw max. (cmos level) 4,194,304 words 4 bits organization silicon gate, cmos, advanced capacitor cell all input and output are ttl compatible 4096 refresh cycles every 65.6 ms early write or oe controlled write capability ras only, cas -before-ras , or hidden refresh fast page mode, read-modify-write capability on chip substrate bias generator for high performance
2 MB8116400B-50/-60 n package (lcc-26p-m09) package and ordering information ?26-pin plastic (300 mil.) soj,order as mb8116400b- pj ?26-pin plastic (300 mil.) tsop-ii with normal bend leads,order as mb8116400b- pftn (fpt-26p-m05) (normal bend) plastic soj package plastic tsop ii package marking side
3 MB8116400B-50/-60 fig. 1 - mb8116400b dynamic ram - block diagram cas ras we oe v cc v ss a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 mode control write clock gen clock gen #2 data in buffer data out buffer column decoder clock gen #1 sense ampl & i/o gate 16,777,216 bit storage cell address buffer & pre- decoder row decoder substrate bias gen dq 1 to dq 4 refresh address counter
4 MB8116400B-50/-60 n pin assignments and descriptions 26-pin soj (top view) row address strobe. write enable. output enable. data input/output v cc +5 volt power supply. v ss circuit ground. v cc dq 1 dq 2 a 11 a 10 a 0 a 1 a 2 a 3 v cc we ras 1 2 3 4 5 19 14 15 8 9 10 11 12 26 25 24 23 22 17 16 621 13 18 1 2 3 4 5 8 9 10 11 12 15 16 17 26 25 24 23 22 19 18 6 13 14 21 (marking side) 1 pin index ras cas oe we 26-pin tsop ii (top view) v ss dq 4 dq 3 a 9 a 8 a 7 a 6 a 5 a 4 v ss cas oe v cc dq 1 dq 2 a 11 a 10 a 0 a 1 a 2 a 3 v cc we ras v ss dq 4 dq 3 a 9 a 8 a 7 a 6 a 5 a 4 v ss cas oe designator function a 0 to a 11 dq 1 to dq 4 address inputs. column address strobe.
5 MB8116400B-50/-60 n functional truth table x : ? or ? * : it is impossible in fast page mode. n functional operation address inputs twenty-two input bits are required to decode any four of 16,777,216 cell addresses in the memory matrix. since only twelve address bits (a 0 to a 11 ) are available, the row and column inputs are separately strobed by ras and cas as shown in figure 1. first, twelve row address bits are input on pins a 0 -through-a 11 and latched with the row address strobe (ras ) then, ten column address bits are input and latched with the column address strobe (cas ). both row and column addresses must be stable on or before the falling edge of ras and cas , respectively. the address latches are of the ?w-through type; thus, address information appearing after t rah (min)+ t t is auto- matically treated as the column address. write enable the read or write mode is determined by the logic state of we . when we is active low, a write cycle is initiated; when we is high, a read cycle is selected. during the read mode, input data is ignored. data input input data is written into memory in either of three basic ways?n early write cycle, an oe (delayed) write cycle, and a read-modify-write cycle. the falling edge of we or cas , whichever is later, serves as the input data-latch strobe. in an early write cycle, the input data (dq 1 -dq 4 ) is strobed by cas and the setup/hold times are referenced to cas because we goes low before cas . in a delayed write or a read-modify-write cycle, we goes low after cas ; thus, input data is strobed by we and all setup/hold times are referenced to the write-enable signal. data output the three-state buffers are ttl compatible with a fanout of two ttl loads. polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes low. when a read or read-modify-write cycle is executed, valid outputs are obtained under the following conditions: t rac : from the falling edge of ras when t rcd (max) is satis?d. t cac : from the falling edge of cas when t rcd is greater than t rcd (max). t aa : from column address input when t rad is greater than t rad (max). t oea : from the falling edge of oe when oe is brought low after t rac , t cac , or t aa . operation mode clock input address input input data refresh note ras cas we oe row column input output standby h h x x high-z read cycle l l h l valid valid valid yes* t rcs 3 t rcs (min) write cycle (early write) l l l x valid valid valid high-z yes* t wcs 3 t wcs (min) read-modify- write cycle llh ? ll ? h valid valid valid valid yes* ras -only refresh cycle l h x x valid high-z yes cas -before-ras refresh cycle l l h x high-z yes t csr 3 t csr (min) hidden refresh cycle h ? l lh ? x l valid yes previous data is kept.
6 MB8116400B-50/-60 the data remains valid until either cas or oe returns to a high logic level. when an early write is executed, the output buffers remain in a high-impedance state during the entire cycle. fast page mode of operation the fast page mode of operation provides faster memory access and lower power dissipation. the fast page mode is implemented by keeping the same row address and strobing in successive column addresses. to satisfy these conditions, ras is held low for all contiguous memory cycles in which row addresses are common. for each fast page of memory, any of 1,024-bits can be accessed and, when multiple mb8116400bs are used, cas is decoded to select the desired memory fast page. fast page mode operations need not be addressed sequentially and combinations of read, write, and/or read-modify-write cycles are permitted.
7 MB8116400B-50/-60 n absolute maximum ratings (see warning) warning: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n recommended operating conditions * : undershoots of up to ?.0 volts with a pulse width not exceeding 20 ns are acceptable. n capacitance (t a = 25 c, f = 1 mhz) parameter symbol value unit voltage at any pin relative to v ss v in , v out ?.5 to +7 v voltage of v cc supply relative to v ss v cc ?.5 to +7 v power dissipation pd 1.0 w short circuit output current ?0 to +50 ma operating temperature t ope 0 to 70 c storage temperature t stg ?5 to +125 c parameter notes symbol min. typ. max. unit ambient operating temp. supply voltage *1 v cc 4.5 5.0 5.5 v 0 c to +70 c v ss 00 0 input high voltage, all inputs *1 v ih 2.4 6.5 v input low voltage, all inputs/outputs* *1 v il ?.3 0.8 v parameter symbol typ. max. unit input capacitance, a 0 toa 11 c in1 ?pf input capacitance, ras , cas , we , oe c in2 ?pf input/output capacitance, dq 1 to dq 4 c dq ?pf
8 MB8116400B-50/-60 n dc characteristics (at recommended operating conditions unless otherwise noted.) note 3 parameter notes symbol conditions values unit min. typ. max. output high voltage v oh i oh = ?.0 ma 2.4 v output low voltage v ol i ol = 4.2 ma 0.4 input leakage current (any input) i i(l) 0 v v in v cc ; 4.5 v v cc 5.5 v; v ss = 0 v; all other pins under test = 0 v ?0 10 m a output leakage current i o(l) 0 v v out v cc ; data out disabled ?0 10 operating current (average power supply current) *2 MB8116400B-50 i cc1 ras & cas cycling; t rc = min ma mb8116400b-60 standby current (power supply current) *2 ttl level i cc2 ras = cas = v ih ma cmos level ras = cas 3 v cc ?.2 v refresh current #1 (average power supply current) *2 MB8116400B-50 i cc3 cas = v ih , ras cycling; t rc = min ma mb8116400b-60 fast page mode current *2 MB8116400B-50 i cc4 ras = v il , cas cycling; t rc = min ma mb8116400b-60 refresh current #2 (average power supply current) *2 MB8116400B-50 i cc5 ras cycling; cas -before-ras ; t rc = min ma mb8116400b-60 90 75 2.0 1.0 90 75 80 70 90 75
9 MB8116400B-50/-60 n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 (continued) no. parameter notes symbol MB8116400B-50 mb8116400b-60 unit min. max. min. max. 1 time between refresh t ref 65.6 65.6 ms 2 random read/write cycle time t rc 90 110 ns 3 read-modify-write cycle time t rwc 126 150 ns 4 access time from ras *6,9 t rac ?0?0ns 5 access time from cas *7,9 t cac ?5?5ns 6 column address access time *8,9 t aa ?5?0ns 7 output hold time t oh 3?ns 8 output buffer turn on delay time t on 0?ns 9 output buffer turn off delay time *10 t off ?3?5ns 10 transition time t t 350350ns 11 ras precharge time t rp 30?0ns 12 ras pulse width t ras 50 100000 60 100000 ns 13 ras hold time t rsh 15?5ns 14 cas to ras precharge time t crp 5?ns 15 ras to cas delay time *11,12 t rcd 17 35 20 45 ns 16 cas pulse width t cas 15?5ns 17 cas hold time t csh 50?0ns 18 cas precharge time (normal) *19 t cpn 7 10 ns 19 row address set up time t asr 0?ns 20 row address hold time t rah 7 10 ns 21 column address set up time t asc 0?ns 22 column address hold time t cah 7 10 ns 23 column address hold time from ras t ar 24?0ns 24 ras to column address delay time *13 t rad 12 25 15 30 ns 25 column address to ras lead time t ral 25?0ns 26 column address to cas lead time t cal 25?0ns 27 read command and set up time t rcs 0?ns 28 read command hold time referenced to ras *14 t rrh 0?ns 29 read command hold time referenced to cas *14 t rch 0?ns 30 write command set up time *15 t wcs 0?ns 31 write command hold time t wch 7 10 ns 32 write hold time from ras t wcr 24?0ns
10 MB8116400B-50/-60 (continued) no. parameter notes symbol MB8116400B-50 mb8116400b-60 unit min. max. min. max. 33 we pulse width t wp 7 10 ns 34 write command to ras lead time t rwl 13?5ns 35 write command to cas lead time t cwl 15?5ns 36 din set up time t ds 0?ns 37 din hold time t dh 7 10 ns 38 data hold time from ras t dhr 24?0ns 39 ras to we delay time *20 t rwd 68?0ns 40 cas to we delay time *20 t cwd 33?5ns 41 column address to we delay time *20 t awd 43?0ns 42 ras precharge time to cas active time (refresh cycles) t rpc 5?ns 43 cas set up time for cas -before- ras refresh t csr 0?ns 44 cas hold time for cas -before- ras refresh t chr 10?0ns 45 we set up time from ras t wsr 0?ns 46 we hold time from ras t whr 10?0ns 47 access time from oe *9 t oea ?5?5ns 48 output buffer turn off delay form oe *10 t oez ?3?5ns 49 oe to ras lead time for valid data t oel 5?ns 50 oe hold time referenced to we *16 t oeh 5?ns 51 oe to data in delay time t oed 13?5ns 52 cas to data in delay time t cdd 13?5ns 53 din to cas delay time *17 t dzc 0?ns 54 din to oe delay time *17 t dzo 0?ns 55 fast page mode ras pulse width t rasp 100000 100000 ns 60 fast page mode read/write cycle time t pc 35?0ns 61 fast page mode read-modify-write cycle time t prwc 73?0ns 62 access time from cas precharge *9,18 t cpa ?0?5ns 63 fast page mode cas precharge time t cp 7 10 ns 64 fast page mode ras hold time from cas precharge t rhcp 30?5ns 65 fast page mode cas precharge to we delay time t cpwd 48?5ns
11 MB8116400B-50/-60 notes: *1. referenced to v ss . *2. i cc depends on the output load conditions and cycle rates; the speci?d values are obtained with the output open. i cc depends on the number of address change as ras = v il , cas = v ih and v il > ?.3 v. i cc1 , i cc3, i cc4 and i cc5 are speci?d at one time of address change during ras = v il and cas = v ih . i cc2 is speci?d during ras =v ih and v il > ?.3 v. *3. an initial pause (ras =cas =vih) of 200 m s is required after power-up followed by any eight ras -only cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of eight cas -before-ras initialization cycles instead of 8 ras cycles are required. *4. ac characteristics assume t t = 5 ns. *5. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also transition times are measured between v ih (min) and v il (max). *6. assumes that t rcd t rcd (max), t rad t rad (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will be increased by the amount that t rcd exceeds the value shown. refer to fig. 2 and 3. *7. if t rcd 3 t rcd (max), t rad 3 t rad (max), and t asc 3 t aa - t cac - t t , access time is t cac . *8. if t rad 3 t rad (max) and t asc t aa - t cac - t t , access time is t aa . *9. measured with a load equivalent to two ttl loads and 100 pf. *10. t off and t oez is speci?d that output buffer change to high-impedance state. *11. operation within the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is speci?d as a reference point only; if t rcd is greater than the speci?d t rcd (max) limit, access time is controlled exclusively by t cac or t aa . *12. t rcd (min) = t rah (min)+ 2 t t + t asc (min). *13. operation within the t rad (max) limit ensures that t rac (max) can be met. t rad (max) is speci?d as a reference point only; if t rad is greater than the speci?d t rad (max) limit, access time is controlled exclusively by t cac or t aa . *14. either t rrh or t rch must be satis?d for a read cycle. *15. t wcs is speci?d as a reference point only. if t wcs 3 t wcs (min) the data output pin will remain high-z state through entire cycle. *16. assumes that t wcs < t wcs (min). *17. either t dzc or t dzo must be satis?d. *18. t cpa is access time from the selection of a new column address (that is caused by changing cas from ? to ??. therefore, if t cp is long, t cpa is longer than t cpa (max). *19. assumes that cas -before-ras refresh. *20. t wcs , t cwd , t, rwd and t awd are not restrictive operating parameters. they are included in the data sheet as an electrical characteristic only. if t wcs > t wcs (min), the cycle is an early write cycle and dq pin will maintain high-impedance state thoughout the entire cycle. if t cwd > t cwd (min), t rwd > t rwd (min), and t awd > t awd (min), the cycle is a read modify-write cycle and data from the selected cell will appear at the dq pin. if neither of the above conditions is satis?d, the cycle is a delayed write cycle and invalid data will appear the dq pin , and write operation can be executed by satisfying t rwl , t cwl , and t ral speci?ations.
12 MB8116400B-50/-60 t rac (ns) t rcd (ns) fig. 2 ? t rac vs. t rcd fig. 3 ? t rac vs. t rad 100 90 80 70 60 20 30 40 50 60 70 50 60 ns version 50 ns version t rad (ns) t rac (ns) 60 ns version 100 90 80 70 60 50 50 ns version 20 30 40 50 60 70 t cp (ns) t cpa (ns) 60 ns version 60 50 40 30 50 ns version 10 20 30 40 50 60 fig. 4 ? t cpa vs. t cp
13 MB8116400B-50/-60 t dzc row add valid data high-z high-z column add description to implement a read operation, a valid address is latched in by the ras and cas address strobes and with we set to a high level and oe set to a low level, the output is valid once the memory access time has elapsed. the access time is determined by ras (t rac ), cas (t cac ), oe (t oea ) or column addresses (t aa ) under the following conditions: if t rcd > t rcd (max), access time = t cac . if t rad > t rad (max), access time = t aa . if oe is brought low after t rac , t cac , or t aa (whichever occurs later), access time = t oea . however, if either cas or oe goes high, the output returns to a high-impedance state after t oh is satis?d. fig. 5 ? read cycle ras v ih v il v ih v il v ih v il v ih v il v oh v ol cas we dq (output) a 0 to a 11 v oh v ol dq (input) v ih v il oe t rc t ras t crp t csh t rcd t rsh t cas t rp t rad t asr t rah t asc t cah t ral t cal t cdd t oel t rcs t rrh t rch t aa t cac t rac t on t oea t oez t dzo t on t oh t oed t off t oh ? or ? level (excluding address and dq) ? or l level, ? ? l or ? ? h transition (address and dq)
14 MB8116400B-50/-60 row valid data i n add column add high-z cas description a write cycle is similar to a read cycle except we is set to a low state and oe is a ? or ? signal. a write cycle can be implemented in either of three ways?arly write, oe write (delayed write), or read-modify-write. during all write cycles, timing parameters t rwl , t cwl and t ral must be satis?d. in the early write cycle shown above t wcs satis?d, data on the dq pin is latched with the falling edge of cas and written into memory. fig. 6 ? early write cycle (oe = ? or ?? ras a 0 to a 11 we dq (input) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol dq (output) t rc t ras t csh t rp t rsh t rcd t crp t cas t ar t asr t rah t asc t cah t wcr t wcs t wch t dhr t ds t dh t ral t rad t cal t cwl t wp t rwl ? or ? level (excluding address and dq) ? or l level, ? ? l or ? ? h transition (address and dq)
15 MB8116400B-50/-60 valid data i n col row add add high-z high-z high-z description in the oe (delayed write) cycle, t wcs is not satis?d ; thus, the data on the dq pins is latched with the falling edge of we and written into memory. the output enable (oe ) signal must be changed from low to high before we goes low (t oed + t ds ). fig. 7 ? oe (delayed write cycle) v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il ras a 0 to a 11 we dq (input) oe v oh v ol dq (output) cas t rc t ras t crp t rp t csh t cas t rsh t rcd t asr t rah t asc t cah t rwd t wch t cwl t rwl t wp t ds t dh t dzc t oed t cac t rac t aa t oez t oeh t rad t cwd t awd t dzo t oea t ral invalid data ? or ? level (excluding address and dq) ? or l level, ? ? l or ? ? h transition (address and dq)
16 MB8116400B-50/-60 valid data i n col row add add high-z high-z valid high-z fig. 8 ? read-modify-write-cycle description the read-modify-write cycle is executed by changing we from high to low after the data appears on the dq pins. in the read- modify-write cycle, oe must be changed from low to high after the memory access time. t rp t rwc t ras t crp t rcd t rad t asr t rah t asc t cah t rwd t cwl t rwl t awd t cwd t rcs t dzc t rac t ds t wp t dh t oeh t oed t cac t aa t on t oea t dzo t oez v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il ras a 0 to a 11 we dq (input) oe v oh v ol dq (output) cas t csh t cas t rsh t ral ? or ? level (excluding address and dq) ? or l level, ? ? l or ? ? h transition (address and dq)
17 MB8116400B-50/-60 col row add add col add col add high-z high-z high-z description the fast page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the access time is determined by t cac , t aa , t cpa , or t oea , which ever one is the latest in occurring. fig. 9 ? fast page mode read cycle t rcd t rasp t rp t rasp t rhcp t rsh t cas t pc t cp t csh t rad t crp t cas t rrh t cah t asc t ral t cah t asc t asc t ar t asr t rah t rcs t rch t rcs t rch t rcs t rch t dzc t cpa t oel t dzo t dzo t off t oh t on t cac t cac t dzo t on t rac t aa t aa t oez t oed v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il ras a 0 to a 11 we dq (input) oe v oh v ol dq (output) cas t cah t dzc t dzc t oh t oed t oea t oez t oea t off high-z valid data ? or ? level (excluding address and dq) ? or l level, ? ? l or ? ? h transition (address and dq)
18 MB8116400B-50/-60 t cah high-z valid data valid data valid data col row add add col add col add fig. 10 ? fast page mode write cycle (oe = ? or ?? description the fast page mode write cycle is executed in the same manner as the fast page mode read cycle except the states of we and oe are reversed. data appearing on the dq pins is latched on the falling edge of cas and written into memory. during the fast page mode write cycle, including the delayed (oe ) write and read-modify-write cycles, t cwl must be satis?d. t rasp t rsh t rp t rhcp t ar t cp t pc t rcd t crp t csh t cas t wch t cas t ral t cah t asc t asc t rad t asc t cah t rah t asr v ih v il v ih v il v ih v il v ih v il v ih v il ras a 0 to a 11 we dq (input) v oh v ol dq (output) cas t wcr t wcs t wch t cwl t wp t dhr t ds t dh t wp t ds t dh t ds t dh t rwl t wp t cwl t cwl t wch t wcs t wcs ? or ? level (excluding address and dq) ? or l level, ? ? l or ? ? h transition (address and dq)
19 MB8116400B-50/-60 col row add. add col add col add valid valid valid high-z fig. 11 ? fast page mode oe write cycle description the fast page mode oe (delayed) write cycle is executed in the same manner as the fast page mode write cycle except for the states of we and oe . input data on the dq pins are latched on the falling edge of we and written into memory. in the fast page mode delayed write cycle, oe must be changed from low to high before we goes low (t oed + t ds ). t rasp t rsh t rp t rhcp t pc t crp t rcd t csh t cas t rad t cas t ral t rwl t cah t asc t cah t asc t cah t cwl t asc t rah t ar t wp t cwl t cwl t rcs t cpwd t rac t dzc t oeh t oed t dh v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il ras a 0 to a 11 we dq (input) oe v oh v ol dq (output) cas t asr t wp t wp t ds t dh t ds t oez t cac t aa t oeh t oez t oez t oea t oea t oea t dzo t cac t oed t oed t aa t aa t cac t dh t ds t cp t oeh invalid data ? or ? level (excluding address and dq) ? or l level, ? ? l or ? ? h transition (address and dq)
20 MB8116400B-50/-60 t asc t cah valid valid valid col row add add col add col add high-z fig. 12 ? fast page mode read-modify-write cycle description during the fast page mode of operation, the read-modify-write cycle can be executed by switching we from high to low after input date appears at the dq pins during a normal cycle. t rasp t rp t ral t cas t rad t csh t crp t rcd t cas t cp t cah t rwl t cwl t oed t asc t asc t cah t ds t rah t asr t rsh v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il ras a 0 to a 11 we dq (input) oe v oh v ol dq (output) cas t cwl t rcs t wp t rcs t cpwd t wp t cwl t rcs t dh t ds t dh t dh t ds t wp t cac t aa t on t oez t oea t cpa t oeh t oez t oea t on t aa t cac t oed t dzc t dzo t prwc valid data ? or ? level (excluding address and dq) ? or l level, ? ? l or ? ? h transition (address and dq)
21 MB8116400B-50/-60 high-z high-z row address fig. 13 ? ras -only refresh (we = oe = ? or ?? fig. 14 ? cas -before-ras refresh (addresses = oe = ? or ?? description refresh of ram memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 4096 row addresses every 65.6-milliseconds. three refresh modes are available: ras -only refresh, cas -before-ras refresh, and hidden refresh. ras -only refresh is performed by keeping ras low and cas high throughout the cycle; the row address to be refreshed is latched on the falling edge of ras . during ras -only refresh, d out pin is kept in a high-impedance state. description cas -before-ras refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. if cas is held low for the speci?d setup time (t csr ) before ras goes low, the on-chip refresh control clock generators and refresh address counter are enabled. an internal refresh operation automatically occurs and the refresh address counter is internally incremented in preparation for the next cas -before-ras refresh operation. t ras t rc t rp t rpc t rah t asr t crp t off t oh t rc t rp t ras t cpn t csr t chr t rpc t off t oh v ih v il v ih v il v ih v il ras a 0 to a 11 v oh v ol dq (output) cas v ih v il v ih v il v ih v il ras we cas v oh v ol dq (output) t whr t wsr ? or ? level (excluding address and dq) ? or l level, ? ? l or ? ? h transition (address and dq) ? or ? level (excluding address and dq) ? or l level, ? ? l or ? ? h transition (address and dq)
22 MB8116400B-50/-60 column row address address valid data out high-z high-z fig. 15 ? hidden refresh cycle description a hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of cas and cycling ras . the refresh row address is provided by the on-chip refresh address counter. this eliminates the need for the external row address that is required by drams that do not have cas -before-ras refresh capability. t rc t ras t ras t rc t rp t oel t rcd t rsh t rad t chr t rp t crp t rah t asr t asc t ral t cah t rcs t rrh t aa t rac t cac t dzc t cdd t whr t oh t off t dzo t oea t on t oez t oed t ar v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il ras a 0 to a 11 we dq (input) oe v oh v ol dq (output) cas t wer ? or ? level (excluding address and dq) ? or l level, ? ? l or ? ? h transition (address and dq)
23 MB8116400B-50/-60 high-z fig. 16 ? test mode set cycle (a 0 - a 11 , oe = ? or ?? description test mode ; the purpose of this test mode is to reduce device test time to one sixteenth of that required to test the device conventionally. the test mode function is entered by performing a we and cas -before-ras (wcbr) refresh for the entry cycle. in the test mode, read and write operations are executed in units of sixteenth bits which are selected by the address combination of ca0 and ca1. in the write mode, data is written into sixteenth cells simultaneously. but the data must be input from dq 1 only. in the read mode, the data of sixteenth cells at the selected addresses are read out from dq and checked in the following manner. when the sixteenth bits are all ? or all ?? a ? level is output. when the sixteenth bits show a combination of ? and ?? a ? level is output. the test mode function is exited by performing a ras -only refresh or a cas -before-ras refresh for the exit cycle. in test mode operation, the following parameters are delayed approximately 10 ns from the speci?d value in the data sheet t rc , t rwc , t rac , t cac , t aa , t ras , t rsh , t cas , t csh , t ral , t cal , t rwd , t cwd , t awd , t cpwd , t rhcp . t ras t rc t cpn t chr t csr t rp t whr t oh t off v ih v il v ih v il v ih v il ras we v oh v ol d out cas t wsr ? or ? level (excluding address and dq) ? or l level, ? ? l or ? ? h transition (address and dq)
24 MB8116400B-50/-60 high-z high-z high-z valid data in column address cas fig. 17 ? cas -before-ras refresh counter test cycle parameter unit ns no. min. (at recommended operating conditions unless otherwise noted.) symbol ns 35 92 93 94 ns 63 ns 45 ns 45 MB8116400B-50 access time from cas column address hold time cas to we delay time cas pulse width ras hold time note. assumes that cas -before-ras refresh counter test cycle only. v ih v il v ih v il ras a 0 to a 11 v ih v il v ih v il v ih v il v oh v ol v ih v il we dq (input) oe 91 90 t fcac t fcah t fcwd t fcas t frsh description a special timing sequence using the cas -before-ras refresh counter test cycle provides a convenient method to verify the functionality of cas -before-ras refresh circuitry. if, after a cas -before-ras refresh cycle cas makes a transition from high to low while ras is held low, read and write operations are enabled as shown above. row and column addresses are de?ed as follows: row address: bits a 0 through a 11 are de?ed by the on-chip refresh counter. column address: bits a 0 through a 11 are de?ed by latching levels on a 0 to a 11 at the second falling edge of cas . the cas -before-ras counter test procedure is as follows ; 1) initialize the internal refresh address counter by using 8 ras only refresh cycles. 2) use the same column address throughout the test. 3) write ? to all 4096 row addresses at the same column address by using normal write cycles. 4) read ? written in procedure 3) and check; simultaneously write ? to the same addresses by using cas -before-ras refresh counter test (read-modify-write cycles). repeat this procedure 4096 times with addresses generated by the internal refresh address counter. 5) read and check data written in procedure 4) by using normal read cycle for all 4096 memory locations. 6) reverse test data and repeat procedures 3), 4), and 5). dq (output) t frsh t rp t chr t csr t cp t fcas t fcah t asc t rcs t cwl t rwl t wp t ds t dh t dzc t oed t fcac t oeh t oez t oea t on t dzo t fcwd t ral t wsr t whr max. 45 min. 35 70 50 50 mb8116400b-60 max. 50 valid data ? or ? level (excluding address and dq) ? or l level, ? ? l or ? ? h transition (address and dq)
25 MB8116400B-50/-60 n package dimensions (suf?: -pj) +0.25 C0.20 +.010 C.008 C0.02 +0.05 C.001 +.002 * details of "a" part 0.81(.032)max 0.430.10 (.017.004) 0.10(.004) 2.60(.102)nom r0.81(.032)typ 3.50 .138 (.270.010) 6.860.25 0.20 .008 index (.339.005) 8.600.13 nom (.300) 7.62 13 8 6 1 14 19 21 26 1.270.13 (.050.005) 17.150.13(.675.005) 15.24(.600)ref 0.64(.025)min 2.80(.110)nom lead no. "a" 1994 fujitsu limited c26059s-3c-1 c dimensions in millimeters (inches) 26-lead plastic leaded chip carrier (case no.: lcc-26p-m09) * this dimension excludes resin protrusion. (each side: .015(.0060) max.)
26 MB8116400B-50/-60 n package dimensions (continued) (suf?: -pftn) 26-lead plastic flat package (case no.: fpt-26p-m05) 1.150.05(.045.002) lead no. (.005.002) 0.1250.05 8.220.20 (.324.008) (.020.004) 0.500.10 (.363.008) 9.220.20 (.300.004) 7.620.10 (stand off) 0.05(.002)min * 0.21(.008) m ref 15.24(.600) 0.10(.004) typ 1.27(.050) (.675.004) 17.140.10 (.016.004) 0.400.10 details of "a" part 0.25(.010) 0.15(.006) max 0.50(.020) max 0.15(.006) index "a" 1 6 8 13 14 19 21 26 1994 fujitsu limited f26005s-2c-1 c dimensions in millimeters (inches) * this dimension excludes resin protrusion. (each side: .015(.0060) max.)
24 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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